The static random access memory (referred to as SRAM hereinafter) is the main stream of the on-chip memories to be mounted on an LSI together with other parts. In spite of this, the SRAM, since it is composed of six transistors, requires a large space for disposing memory cells, encountering a problem of mounting space when it employed to be mounted on an LSI together with other parts.
There is another method where a dynamic random access memory (referred to as DRAM hereinafter) is mounted on an LSI together with other parts. The DRAM that is composed of a transistor and a capacitor has small memory cells in disposing area, leading to a comparatively large capacity. The DRAM, however, has disadvantages in which its cycle time is slower than that of the SRAM and the DRAM is required to be refreshed, causing it rather complicated and troublesome to control the DRAM. Of these problems, the cycle time, as it has been well known, can be speeded up by reducing the number of memory cells disposed on each bit line thereof, while the refreshing cannot be hidden completely from external.
Recently, however, U.S. Pat. No. 5,999,474 has disclosed a method that can hide refresh operations with use of DRAM memory cells. In the case of the semiconductor memory described in the USP (referred to as 1T-SRAM hereinafter according to the USP), the semiconductor memory is composed of a DRAM divided into a plurality of banks, an SRAM having a capacity equivalent to that of a bank, and the SRAM portion is used as a cache memory. While the cache memory is being hit, the DRAM is in the idle state (no access is done thereto). The idle time is used for a dedicated controller to complete the refresh operation in the DRAM. This eliminates the need of external control for the refresh operation. In addition, the method is constituted such that a direct mapped caching scheme having easy control of the cache memory can be employed to control the cache memory; and the cache memory is connected to the DRAM via a dual port composed of a read data bus and a write data bus. The constitution permits of writing back to the cache memory from the DRAM as well as of doing the fetch on write operation from the DRAM to the cache memory just in one cycle. Also with this constitution, even when an access to the cache memory is decided as a miss hit, for example, during a read operation, the target data can be read immediately from the DRAM, thereby the data can be output in one cycle after the address input. This makes it possible to expect that an on-chip memory can be easily controlled with use of a DRAM composed of a cache memory having a capacity equivalent to that of a bank, and multiple banks as described above.
Nevertheless, it has been found by examining the above described known invention that it would be difficult to hide refresh operations under a predetermined condition where the data width differs between the cache line of the cache memory provided in the 1T-SRAM differs and the data bus that connects the 1T-SRAM to an external device.
A cache memory usually comprises a plurality of entries, each consisting of a data part used to store data and a tag part used to store the address of the data part. Each entry is provided with a dirty bit used to denote updating of stored data. When data is written in an entry, thereby the data in the entry is updated, this dirty bit is set. When the data in the entry is to be replaced, the data is written back into the main memory, thereby the data coherency is kept between the cache memory and the main memory. The method is referred to as the write-back method.
In the cache memory of said USP, when a write access is requested to an entry that has retained dirty data and the access is decided as a cache miss (a different tag address in the same entry is hit), the data is written back from the cache memory to the DRAM, then allocated (fetch on write) from the DRAM to the accessed cache line to keep the data coherency between the cache memory and the DRAM In other words, the access is controlled as if it were a write-back operation performed by the write allocation method. According to the configuration of the above invention, each bank address of the DRAM is assigned to a cache memory tag. Therefore, the write-back operation and the fetch on write operation are executed in different two banks. For example, when an access related to the bank B is done to an entry while the data related to a bank A is stored in the entry, the data is written back in the bank A and a fetch on write operation is done in the bank B respectively. After that, when an access related to the bank A is done for the same entry, a write-back access to the bank B is done and a fetch-on write operation is done for the bank A. Consequently, for example, when write access cache misses occurs consecutively in the same entry, the two banks in the DRAM come to be kept accessed. In other words, no refresh operation can be done in those two banks, thereby some data in the DRAM might be damaged.